Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DUNE: a multi-layer gridless routing system with wire planning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Performance driven multi-level and multiway partitioning with retiming
Proceedings of the 37th Annual Design Automation Conference
Timing-driven routing for symmetrical array-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
DAC '78 Proceedings of the 15th Design Automation Conference
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
A New Timing-Driven Multilayer MCM/IC Routing Algorithm
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Multilevel routing with antenna avoidance
Proceedings of the 2004 international symposium on Physical design
Optical proximity correction (OPC): friendly maze routing
Proceedings of the 41st annual Design Automation Conference
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing by new approximation algorithms for multicommodity flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MR: a new framework for multilevel full-chip routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel framework for multilevel full-chip gridless routing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the 2006 international symposium on Physical design
Novel full-chip gridless routing considering double-via insertion
Proceedings of the 43rd annual Design Automation Conference
Novel wire density driven full-chip routing for CMP variation control
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Predictive formulae for OPC with applications to lithography-friendly routing
Proceedings of the 45th annual Design Automation Conference
A novel wire-density-driven full-chip routing system for CMP variation control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Predictive formulae for OPC with applications to lithography-friendly routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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To handle modern routing with nanometer effects, we need to consider designs of variable wire widths and spacings, for which gridless routers are desirable due to their great flexibility. The gridless routing is much more difficult than the grid-based one because the solution space of gridless routing is significantly larger than that of grid-based one. In this paper, we present the first multilevel, full-chip gridless detailed router. The router integrates global routing, detailed routing, and congestion estimation together at each level of the multilevel routing. It can handle non-uniform wire widths and consider routability and optical proximity correction (OPC). Experimental results show that our approach obtains significantly better routing solutions than previous works. For example, for a set of 11 commonly used benchmark circuits, our approach achieves 100% routing completion for all circuits while the famous state-of-the-art three-level routing and multilevel routing (multilevel global routing + flat detailed routing) cannot complete routing for any of the circuits. Besides, experimental results show that our multilevel gridless router can handle non-uniform wire widths efficiently and effectively (still maintain 100% routing completion for all circuits). In particular, our OPC-aware multilevel gridless router archives an average reduction of 11.3% pattern features and still maintains 100% routability for the 11 benchmark circuits.