Post global routing crosstalk risk estimation and reduction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Congestion driven quadratic placement
DAC '98 Proceedings of the 35th annual Design Automation Conference
A timing-constrained algorithm for simultaneous global routing of multiple nets
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A New Timing-Driven Multilayer MCM/IC Routing Algorithm
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Timing-constrained congestion-driven global routing
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacity constraints as well as achieving higher routability and good routing flexibility. The initial solution consists of nets routed independently by the SERT-C algorithm which minimizes the Elmore delay at critical sink of a Steiner tree. Then, all the nets with the most congested edge, i.e., the edge with maximum flow, are ripped up and rerouted by using an iterative hierarchical approach. FOT each iteration, a window is specified according to the span of the ripped-up nets or an upper bound if the span is too large. Rerouting is done hierarchically within the window by using integer programming to optimize the flow uniformity. The algorithm terminates when the flow uniformity can not be further improved. The algorithm has been implementedand interfaced with a placement tool. Experiments show that the algorithm can improve the pow uniformity by 19% to 97%. The final results include the number of routing layers needed to complete the routing. Thus, the method is also useful in determining the required number of layers for packaging design using multi-chip models.