New performance-driven FPGA routing algorithms
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Timing optimization of FPGA placements by logic replication
Proceedings of the 40th annual Design Automation Conference
Deterministic network coding by matrix completion
SODA '05 Proceedings of the sixteenth annual ACM-SIAM symposium on Discrete algorithms
The encoding complexity of network coding
IEEE/ACM Transactions on Networking (TON) - Special issue on networking and information theory
Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space
Proceedings of the 2007 international symposium on Physical design
Network coding for routability improvement in VLSI
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
The Lee Path Connection Algorithm
IEEE Transactions on Computers
Network coding: a computational perspective
IEEE Transactions on Information Theory
IEEE Transactions on Information Theory
On-chip bidirectional wiring for heavily pipelined systems using network coding
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Efficient congestion mitigation using congestion-aware steiner trees and network coding topologies
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Design and evaluation of random linear network coding Accelerators on FPGAs
ACM Transactions on Embedded Computing Systems (TECS)
Integration, the VLSI Journal
Reconfigurable and parallelized network coding decoder for VANETs
Mobile Information Systems
Hi-index | 0.00 |
With current technology trends, FPGA routing is an important problem, since routing in FPGAs contributes significantly to delay and resource utilization, as compared to the logic portion of FPGAs. In this paper we improve the FPGA routing characteristics by applying the technique of network coding. This relatively new technique was developed in the context of communication networks, and proven to improve network throughput, reliability, etc. To the best of our knowledge, this paper is the first to apply network coding to improve FPGA routing. Our preliminary results are implemented in the VPR 4.30 tool suite. We demonstrate (on average) a 14% reduction in worst case delay, a 3% reduction in wirelength and a healthy reduction in the routing track count on several MCNC benchmark circuits, over the current best known results. By using carefully generated cost models for applying the technique of network coding, we show that this routability improvement is accompanied by a zero percent CLB utilization overhead and