Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

• Authors:

• Takahiro Deguchi;Tetsushi Koide;Shin'ichi Wakabayashi

• Affiliations:

• Faculty of Engineering, Hiroshima University, 4-1, Kagamiyama 1 chome, Higashi-Hiroshima, 739-8527, Japan;VLSI Design and Education Center, The University of Tokyo, 7-3-1, Hongo, Bunkyo-ku, Tokyo 113-8656, Japan;Faculty of Engineering, Hiroshima University, 4-1, Kagamiyama 1 chome, Higashi-Hiroshima, 739-8527, Japan

• Venue:
• ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
• Year:
• 2000