Quantified suboptimality of VLSI layout heuristics
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Pre-layout estimation of individual wire lengths
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Why interconnect prediction doesn't work
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Improved Effective Capacitance Computations for Use in Logic and Layout Optimization
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Combining Technology Mapping with Post-Placement Resynthesis for Performance Optimization
ICCD '98 Proceedings of the International Conference on Computer Design
Shield count minimization in congested regions
Proceedings of the 2002 international symposium on Physical design
Gain-based technology mapping for discrete-size cell libraries
Proceedings of the 40th annual Design Automation Conference
Fast parallel prefix logic circuits for n2n round-robin arbitration
Microelectronics Journal
Power benefit study for ultra-high density transistor-level monolithic 3D ICs
Proceedings of the 50th Annual Design Automation Conference
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Wire load models (WLMs) are generally perceived to be inaccurate and inadequate for good optimization. The traditional wisdom is that accuracy of WLMs will worsen as die sizes expand and feature sizes shrink, and as wire loads become less predictable and more dominant over pin loads. In many industry white papers and academic works, the weaknesses of WLMs are used to motivate the unification of logic synthesis and physical layout into a single tool. We believe, however, that care must be taken in how we derive our motivations for new flows. In previous studies, evidence against WLMs was generally anecdotal or based on limited data (e.g., from a single design). Today, the maturation of Cadence Design Systems' PKS design tool affords us a unique opportunity to study WLMs in greater depth, and to quantify the timing improvements achieved by the unification of synthesis and layout. Using PKS, we have performed extensive experiments on fifteen real industry test cases. Our results confirm much of the conventional wisdom about WLMs, but also indicate that WLMs probably can still perform a useful function in the design flow.