A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
On the relevance of wire load models
Proceedings of the 2001 international workshop on System-level interconnect prediction
A synthesis oriented omniscient manual editor
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
SafeResynth: A new technique for physical synthesis
Integration, the VLSI Journal
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On the decreasing significance of large standard cells in technology mapping
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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This paper presents an innovative two-phase approach which combines technology mapping with logic resynthesis for minimizing the post-placement delays. The main idea is to alleviate the effect of inaccurate delay models in the mapping phase and to use a more accurate post-placement delay model in the logic resynthesis phase. To achieve this, our mapping phase disables the operations which may provide unpredictable effects on the circuit performance and leave them to be solved in the resynthesis phase. In the resynthesis phase, a post-placement delay model is extracted from the placement of the circuits. The techniques developed in our resynthesis algorithm are remapping, signal substitution, and gate duplication. Based on a wide range of benchmark examples, experimental results show that our approach provides 17% reduction in terms of post-placement delays when compared with SIS-1.2.