Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Formulae and applications of interconnect estimation considering shield insertion and net ordering
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Analysis and Avoidance of Cross-Talk in On-Chip Buses
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
Preventing Crosstalk Delay using Fibonacci Representation
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Exploiting Crosstalk to Speed up On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Efficient on-chip crosstalk avoidance CODEC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A bit-stuffing algorithm for crosstalk avoidance in high speed switching
INFOCOM'10 Proceedings of the 29th conference on Information communications
Efficient CODEC designs for crosstalk avoidance codes based on numeral systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosstalk avoidance codes for 3D VLSI
Proceedings of the Conference on Design, Automation and Test in Europe
Fibonacci codes for crosstalk avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this work, we present a CODEC design for the forbidden transition free crosstalk avoidance code. Our mapping and coding scheme is based on the Fibonacci numeral system and the mathematical analysis shows that all numbers can be represented by FTF vectors in the Fibonacci numeral system (FNS). The proposed CODEC design is highly efficient, modular and can be easily combined with a bus partitioning technique. We also investigate the implementation issues and our experimental results show that the proposed CODEC complexity is orders of magnitude better compared to the brute force implementation. Compared to the best existing approaches, we achieve a 17% improvement in logic complexity. A high speed design can be achieved through pipelining.