Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing bus delay in submicron technology using coding
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
Low Power Digital CMOS Design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Signal Integrity Issues and Printed Circuit Board Design
Signal Integrity Issues and Printed Circuit Board Design
A Crosstalk Aware Interconnect with Variable Cycle Transmission
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Minimization of Crosstalk Noise, Delay and Power Using a Modi.ed Bus Invert Technique
Proceedings of the conference on Design, automation and test in Europe - Volume 2
High-Speed Circuit Board Signal Integrity
High-Speed Circuit Board Signal Integrity
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method
DELTA '06 Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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Inductance effects cannot be neglected in global interconnect lines as well as in circuits operating at higher frequencies. This paper presents a new spatio-temporal bus-encoding technique to minimize simultaneous switching noise as well as reduce delay and power dissipation in on-chip buses where inductance effects are dominating. Simulation experiments are carried out to find out the delay and SSN reduction for interconnect lines of different lengths (2mm, 5mm and 10mm) at various technology nodes (180nm, 130nm, 90nm and 65nm). Results obtained show that that the proposed bus-encoding scheme provides a delay reduction of about 54% to 73% with respect to the worst case delay. In addition, encoding is combined with wire shaping and its impact on further delay reduction is observed to be 4% to 26%. Further, when encoding was combined with wire shaping and repeater insertion, an additional delay reduction of 9% to 33% is observed. Concerning SSN, the encoding scheme is tested with various SPEC'95 benchmarks and it is found that SSN is reduced by about 33% on an average compared with the un-encoded data. Finally, energy minimization of about 13% on an average is achieved by the application of new spatio-temporal encoding scheme as reflected by the SPEC'95 bench mark tests.