Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Steady-state simulation of queueing processes: survey of problems and solutions
ACM Computing Surveys (CSUR)
The turn model for adaptive routing
Journal of the ACM (JACM)
Journal of Complexity - Special issue for the Foundations of Computational Mathematics conference, Rio de Janeiro, Brazil, Jan. 1997
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
A Statistical Traffic Model for On-Chip Interconnection Networks
MASCOTS '06 Proceedings of the 14th IEEE International Symposium on Modeling, Analysis, and Simulation
Application Specific Routing Algorithms for Networks on Chip
IEEE Transactions on Parallel and Distributed Systems
Application-aware deadlock-free oblivious routing
Proceedings of the 36th annual international symposium on Computer architecture
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BOFAR: buffer occupancy factor based adaptive router for mesh NoCs
Proceedings of the 4th International Workshop on Network on Chip Architectures
TRACKER: a low overhead adaptive NoC router with load balancing selection strategy
Proceedings of the International Conference on Computer-Aided Design
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
An analytical latency model for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present a system-level Congestion-Aware Routing (CAR) framework for designing minimal deterministic routing algorithms. CAR exploits the peculiarities of the application workload to spread the load evenly across the network. To this end, we first formulate an optimization problem of minimizing the level of congestion in the network and then use the simulated annealing heuristic to solve this problem. The proposed framework assures deadlock-free routing, even in the networks without virtual channels. Experiments with both synthetic and realistic workloads show the effectiveness of the CAR framework. Results show that maximum sustainable throughput of the network is improved by up to 205% for different applications and architectures.