Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Transient-fault recovery for chip multiprocessors
Proceedings of the 30th annual international symposium on Computer architecture
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Exploiting Microarchitectural Redundancy For Defect Tolerance
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Towards on-chip fault-tolerant communication
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks
IEEE Transactions on Computers
IEEE Transactions on Computers
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Yield and Cost Analysis of a Reliable NoC
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-adaptive system for addressing permanent errors in on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A highly resilient routing algorithm for fault-tolerant NoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RAPA: reliability-aware priority arbitration strategy for network on chip
Proceedings of the great lakes symposium on VLSI
Towards graceful aging degradation in NoCs through an adaptive routing algorithm
Proceedings of the 49th Annual Design Automation Conference
Structural Test and Diagnosis for Graceful Degradation of NoC Switches
Journal of Electronic Testing: Theory and Applications
A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
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The aggressive advent in VLSI manufacturing technology has made dramatic impacts on the dependability of devices and interconnects. In the modern manycore system, mesh based Networks-on-Chip (NoC) is widely adopted as on chip communication infrastructure. It is critical to provide an effective fault tolerance scheme on mesh based NoC. A faulty router or broken link isolates a well functional processing element (PE). Also, a set of faulty routers form faulty regions which may break down the whole design. To address these issues, we propose an innovative router-level fault tolerance scheme with spare routers which is different from the traditional microarchitecture-level approach. The spare routers not only provide redundancies but also diversify connection paths between adjacent routers. To exploit these valuable resources on fault tolerant capabilities, two configuration algorithms are demonstrated. One is shift-and-replace-allocation (SARA) and the other is defect-awareness-path-allocation (DAPA) that takes advantage of path diversity in our architecture. The proposed design is transparent to any routing algorithm since the output topology is consistent to the original mesh. Experimental results show that our scheme has remarkable improvements on fault tolerant metrics including reliability, mean time to failure (MTTF), and yield. In addition, the performance of spare router increases with the growth of NoC size but the relative connection cost decreases at the same time. This rare and valuable characteristic makes our solution suitable for large scale NoC design.