Diagnosis of interconnect shorts in mesh NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Control-ready architecture for self-testing in programmable logical matrix structures
Automation and Remote Control
On the design and analysis of fault tolerant NoC architecture using spare routers
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Improving the yield of NoC-based systems through fault diagnosis and adaptive routing
Journal of Parallel and Distributed Computing
A distributed and topology-agnostic approach for on-line NoC testing
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Journal of Electronic Testing: Theory and Applications
A resilient architecture for low latency communication in shared-L1 processor clusters
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes
Microprocessors & Microsystems
Hi-index | 14.98 |
A novel strategy to detect interconnect faults between distinct channels in networks-on-chip is proposed. Short faults between distinct channels in the data, control and communication handshake lines are considered in a cost-effective test sequence for Mesh NoC topologies based on XY routing.