The Case for Lifetime Reliability-Aware Microprocessors
Proceedings of the 31st annual international symposium on Computer architecture
Rescue: A Microarchitecture for Testability and Defect Tolerance
Proceedings of the 32nd annual international symposium on Computer Architecture
Exploiting Structural Duplication for Lifetime Reliability Enhancement
Proceedings of the 32nd annual international symposium on Computer Architecture
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Autonomic Microprocessor Execution via Self-Repairing Arrays
IEEE Transactions on Dependable and Secure Computing
Ultra low-cost defect protection for microprocessor pipelines
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Architecting a reliable CMP switch architecture
ACM Transactions on Architecture and Code Optimization (TACO)
Configurable isolation: building high availability systems with commodity multi-core processors
Proceedings of the 34th annual international symposium on Computer architecture
Online diagnosis of hard faults in microprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Power and reliability management of SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An industrial perspective of power-aware reliable SoC design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
The StageNet fabric for constructing resilient multicore systems
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Evaluating the effects of cache redundancy on profit
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Architectural core salvaging in a multi-core processor for hard-error tolerance
Proceedings of the 36th annual international symposium on Computer architecture
Selective wordline voltage boosting for caches to manage yield under process variations
Proceedings of the 46th Annual Design Automation Conference
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive online testing for efficient hard fault detection
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Necromancer: enhancing system throughput by animating dead cores
Proceedings of the 37th annual international symposium on Computer architecture
Trifecta: a nonspeculative scheme to exploit common, data-dependent subcritical paths
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable thread scheduling and global power management for heterogeneous many-core architectures
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Proceedings of the Conference on Design, Automation and Test in Europe
Improving yield and reliability of chip multiprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
On the design and analysis of fault tolerant NoC architecture using spare routers
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A Metric for Quantifying Similarity between Timing Constraint Sets in Real-Time Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DEFCAM: A design and evaluation framework for defect-tolerant cache memories
ACM Transactions on Architecture and Code Optimization (TACO)
ROSY: recovering processor and memory systems from hard errors
ACM SIGOPS Operating Systems Review
Optimization of reliability and power consumption in systems on a chip
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Viper: virtual pipelines for enhanced reliability
Proceedings of the 39th Annual International Symposium on Computer Architecture
Deconfigurable microprocessor architectures for silicon debug acceleration
Proceedings of the 40th Annual International Symposium on Computer Architecture
Fine-grain voltage tuned cache architecture for yield management under process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
Cost-effective lifetime and yield optimization for NoC-based MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The continued increase in microprocessor clock frequency that hascome from advancements in fabrication technology and reductions infeature size, creates challenges in maintaining both manufacturingyield rates and long-term reliability of devices. Methods based ondefect detection and reduction may not offer a scalable solutiondue to cost of eliminating contaminants in the manufacturingprocess and increasing chip complexity. This paper proposes to usethe inherent redundancy available in existing and future chipmicroarchitectures to improve yield and enable graceful performancedegradation in fail-in-place systems. We introduce a new yieldmetric called performance averaged yield (YPAV) which accounts bothfor fully functional chips and those that exhibit some performancedegradation. Our results indicate that at 250nm we are able toincrease the YPAY of a uniprocessor with only redundant rows in itscaches from a base value of 85% to 98% using microarchitecturalredundancy. Given constant chip area, shrinking feature sizesincreases fault susceptibility and reduces the base YPAY to 60% at50nm, which exploiting microarchitectural redundancy then increasesto 99.6%.