A routing algorithm for random error tolerance in network-on-chip

Authors:
Lei Zhang;Huawei Li;Xiaowei Li
Affiliations:
Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China and Graduate University of Chinese Academy of Sciences, Beijing, ...;Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China;Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Venue:
HCI'07 Proceedings of the 12th international conference on Human-computer interaction: applications and services
Year:
2007

Citing 9
Cited 0

Addressing the system-on-a-chip interconnect woes through communication-based design

Proceedings of the 38th annual Design Automation Conference
On-chip communication architecture for OC-768 network processors

Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach

Interconnection Networks: An Engineering Approach
Networks on Chip: A New Paradigm for Systems on Chip Design

Proceedings of the conference on Design, automation and test in Europe
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Analysis of Error Recovery Schemes for Networks on Chips

IEEE Design & Test
Towards on-chip fault-tolerant communication

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

In DSM and nanometer technology, there will present more and more new fault types, which are difficult to predict and avoid. Applying fault tolerant algorithms to achieve reliable on-chip communication is one of the most important issues of Network-on-Chip (NoC). This paper reviews the main on-chip fault tolerant communication algorithms and then proposes a new routing algorithm with end-to-end feedback. The average transmission latency, power consumption and reliability are compared with other techniques. As experiments show, the proposed algorithm has lower latency, lower power consumption compared with those of others, and it can provide high reliability.