Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Planar-adaptive routing: low-cost adaptive networks for multiprocessors
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
A Cost and Speed Model for k-ary n-Cube Wormhole Routers
IEEE Transactions on Parallel and Distributed Systems
The turn model for adaptive routing
25 years of the international symposia on Computer architecture (selected papers)
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Embedded Robustness IPs for Transient-Error-Free ICs
IEEE Design & Test
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
FOCS '00 Proceedings of the 41st Annual Symposium on Foundations of Computer Science
Testing SoC Interconnects for Signal Integrity Using Boundary Scan
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Quality-of-service and error control techniques for network-on-chip architectures
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Towards on-chip fault-tolerant communication
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Exploring Fault-Tolerant Network-on-Chip Architectures
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
Proceedings of the 43rd annual Design Automation Conference
Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
A methodology for design of application specific deadlock-free routing algorithms for NoC systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Adaptive Deadlock-Free Routing in Multicomputers Using Only One Extra Virtual Channel
ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 01
The Message Flow Model for Routing in Wormhole-Routed Networks
ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 01
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
Proceedings of the conference on Design, automation and test in Europe
A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips
PRDC '07 Proceedings of the 13th Pacific Rim International Symposium on Dependable Computing
XYX: A Power & Performance Efficient Fault-Tolerant Routing Algorithm for Network on Chip
PDP '09 Proceedings of the 2009 17th Euromicro International Conference on Parallel, Distributed and Network-based Processing
Analytic performance modeling of a fully adaptive routing algorithm in the torus
ISPA'05 Proceedings of the Third international conference on Parallel and Distributed Processing and Applications
Energy and reliability oriented mapping for regular Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
| Hi-index | 0.00 |
Use of deep sub-micron VLSI technologies in fabrication of Network on Chips (NoCs) makes the reliability to be one of the first order concerns in the design of these products. This paper proposes and evaluates a methodology that adds reliability to NoC routing algorithms with minimal power and performance overheads. The key idea behind this methodology is to use the concept of complement routing in which two routing algorithms with disjoint sets of allowed turns are incorporated. According to this methodology, while a packet is routed by a routing algorithm, a redundant copy of that packet is routed by the complement of that routing algorithm. This is done by exploiting channels with lower utilization to route redundant packets. To find the complement of the used NoC routing algorithm, an analytical approach based on the channel dependency graph is presented. The methodology is applied to two NoCs using the dimension order and the Duato's routing algorithms. These networks are simulated using an HDL-based NoC simulator along with the Synopsys Power Compiler tool. Results extracted by different traffic generation rates and by different error injection rates confirm that the proposed methodology provides similar reliability improvement in comparison with the flood-based routing algorithms. This methodology also decreases the performance and power consumption overheads as compared to the flood-based routing algorithms.