Testing SoC Interconnects for Signal Integrity Using Boundary Scan

  • Authors:
  • M. H. Tehranipour;N. Ahmed;M. Nourani

  • Affiliations:
  • -;-;-

  • Venue:
  • VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
  • Year:
  • 2003

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Abstract

As the technology is shrinking toward 50 nm and the working frequencyis going into multi gigahertz range, the effect of interconnectson functionality and performance of system-on-chips is becomingdominant. More specifically, distortion (integrity loss) of signalstraveling on high-speed interconnects can no longer be ignored. Inthis paper, we extend the conventional boundary scan architectureto allow testing signal integrity in SoC interconnects. Our extendedJTAG architecture collects and outputs the integrity loss informationusing the enhanced observation cells. The architecture fully complieswith the JTAG standard and can be adopted by any SoC that is IEEE1149.1 compliant. We also propose a simple yet efficient compressionscheme that can be employed by an ATE to minimize the scan-indelivery time.