An efficient zero-skew routing algorithm
DAC '94 Proceedings of the 31st annual Design Automation Conference
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Multi-GHz interconnect effects in microprocessors
Proceedings of the 2001 international symposium on Physical design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
Practical techniques to reduce skew and its variations in buffered clock networks
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Grid-to-ports clock routing for high performance microprocessor designs
Proceedings of the 2011 international symposium on Physical design
HEX: scaling honeycombs is easier than scaling clock trees
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
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Microprocessors typically employ a global grid followed by block-level buffered trees for clock distribution. The trees are connected to the grid by routing wires along reserved tracks. The routing of these clock wires, which present load to the grid, is constrained by delay/slope requirements at inputs of the block-level trees. This leads to a capacitance minimization problem during multiterminal routing, where routes use the reserved tracks and obey the constraints. This paper presents an algorithm that addresses the problem, improving wirelength by 14% over a competitive approach. The algorithm is employed for post-grid clock distribution in a 45 nm technology microprocessor.