VLSI implementation of a distributed algorithm for fault-tolerant clock generation
Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
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To achieve fault tolerance several tasks have to be performed, from fault detection up to recovery procedures. Sophisticated methods for each sub-task were and are still developed, but rarely a complete solution is proposed on circuit level. This paper fills the gap by proposing a concept that combines all required steps to implement fault tolerant digital circuits. The approach is based on asynchronous Four-State Logic (FSL) logic, which belongs to the family of Quasi Delay Insensitive (QDI) circuits. Contrary to conventional approaches, using synchronous logic plus additional hardware and/or software to achieve fault tolerance, we use the inherent properties of FSL for fault detection, fault localization and fault recovery. Only deadlock detection and error mitigation require an enhancement of the conventional FSL design. For this purpose, a monitoring unit has to be added and self-healing cells were developed that can be handled as conventional logic within the design flow. The feasibility of the approach is verified by a first prototype implementation of a fault tolerant adder circuit.