Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing robust threshold gates against soft errors
Microelectronics Journal
An infrastructure for accurate characterization of single-event transients in digital circuits
Microprocessors & Microsystems
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This paper presents an efficient concurrent failure detection method for pipelined asynchronous circuits. We first validate permanent and transient fault modeling in clockless systems. By augmenting the rails to each data channel and adding extra logic to each circuit module, we make pipelined asynchronous circuits achieve fail-stop with respect to hard or soft errors. The experimental evaluations show this method incurs both reasonable hardware cost and low performance overhead.