Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Communication systems engineering
Communication systems engineering
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
PRISM 2.0: A Tool for Probabilistic Model Checking
QEST '04 Proceedings of the The Quantitative Evaluation of Systems, First International Conference
Fundamentals of wireless communication
Fundamentals of wireless communication
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
Application-Level Correctness and its Impact on Fault Tolerance
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Probabilistic Testability Analysis and DFT Methods at RTL
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs
QEST '10 Proceedings of the 2010 Seventh International Conference on the Quantitative Evaluation of Systems
IEEE Transactions on Information Theory
Evaluating the reliability of NAND multiplexing with PRISM
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Soft-Error-Rate-Analysis (SERA) Methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Sources of noise such as quantization, introduce randomness into register transfer level (RTL) designs of complex systems. In previous work, we introduced a formal approach to compute the performance metrics for these designs with high confidence. We defined the performance metrics as properties in a probabilistic temporal logic. We then used probabilistic model checking to verify these properties for RTL and thereby guarantee the statistical performance. In this work, we enhance our previous approach in order to include the effects of permanent and transient faults that may be present in the lower levels of hardware implementation. We then formally analyze the vulnerability of performance of RTL designs to faults that are present at different locations. If a performance requirement is not met, we employ probabilistic model checking with a diagnostic property that can be used to identify the broad cause of performance degradation. In this work, we describe our entire approach by considering RTL designs corresponding to multiple-input-multiple-output (MIMO) communication systems. We illustrate our enhanced approach on the Viterbi decoder which is a nontrivial component of MIMO system designs.