Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger
Journal of Electronic Testing: Theory and Applications
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Technology scaling has led to a reduction in the stored charge in SRAM memories. This has increased their vulnerability to soft errors. Conventional approaches to detect/correct soft errors, such as ECC, have limitation in the number of soft errors that can be tolerated. In this paper, we propose a soft error detection circuit which utilizes a current mirror to translate switching current pulses induced by soft errors into voltage pulses. This pulse is then sensed by a Schmitt trigger to generate an error signal. Our experimental results show that the proposed scheme is tolerant to process variation and results in low power overhead without significantly affecting performance.