Improving testability and soft-error resilience through retiming
Proceedings of the 46th Annual Design Automation Conference
Signature-based SER analysis and design of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Error immune logic for low-power probabilistic computing
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
ERSA: error resilient system architecture for probabilistic applications
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis and optimization of fault-tolerant embedded systems with hardened processors
Proceedings of the Conference on Design, Automation and Test in Europe
Multiple transient faults in combinational and sequential circuits: a systematic approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Circuit-level design approaches for radiation-hard digital electronics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Assessing system vulnerability using formal verification techniques
MEMICS'11 Proceedings of the 7th international conference on Mathematical and Engineering Methods in Computer Science
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Transient or soft errors are an increasing problem in mainstream microelectronics. We propose a framework for modeling transient-error tolerance (TET) in logic circuits. We classify transient errors as critical or non-critical according to their impact on circuit behavior, such as their ability to disturb the internal state for specified periods of time. We introduce a metric called the critical soft-error rate (CSER) as an alternative to conventional SER, and present some analysis strategies based on CSER. This approach employs a new single transient fault (STF) model, which is defined in terms of a temporary stuck-at fault and its associated circuit state. Although basically technology-independent, STFs can be extended with low-level physical attributes. With STFs, we can estimate the transient error probability perr of a circuit's nodes, as well as various measures of error susceptibility and TET. We demonstrate the use of STFs with combinational and sequential circuits, including several types of adders. We also present a systematic hardening strategy that uses perr as a guide to improving TET.