An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
Journal of Electronic Testing: Theory and Applications
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Journal of Electronic Testing: Theory and Applications
A New Approach to the Analysis of Single Event Transients in VLSI Circuits
Journal of Electronic Testing: Theory and Applications
Soft error rate estimation and mitigation for SRAM-based FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Boosting software fault injection for dependability analysis of real-time embedded applications
ACM Transactions on Embedded Computing Systems (TECS)
A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs
Journal of Electronic Testing: Theory and Applications
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In this paper, approaches using Run-Time Reconfiguration (RTR) for fault injection in programmable systems are introduced. In FPGA-based systems, an important characteristic is the time to reconfigure the hardware. With novel FPGA families, (e.g. Virtex, A T6000) it is possible to reconfigure the hardware partially in run-time. Important timesavings can be achieved when taking advantage of this characteristic for fault injection as only a small part of the device must be reconfigured.