Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels

Authors:
A. Ammari;R. Leveugle;M. Sonza-Reorda;M. Violante
Affiliations:
-;-;-;-
Venue:
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Year:
2003

Citing 0
Cited 2

Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation

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Statistical fault injection: quantified error and confidence

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Abstract

Methods allowing a designer to perform early dependability analyses aim either at classifying the faults according to their main potential effect, or at analyzing more in depth the error propagation paths in the circuit. In the two cases, these methods can be applied at several description levels, starting from the behavioral level down to the gate level with back-annotation data. This paper compares results obtained at RT and gate levels. The advantages of combining an error propagation path analysis and a classification are also discussed.