Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Journal of Electronic Testing: Theory and Applications
Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Journal of Electronic Testing: Theory and Applications
Enhancement of fault injection techniques based on the modification of VHDL code
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical fault injection: quantified error and confidence
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents the principles of two different approaches for the study of the effect of transient bit flips on the behavior of processor-based digital architectures: one of them based on the on-line "injection" and execution of pieces of code (called CEU codes) using a suitable hardware architecture, while the other is performed using a behavioral level processor description, being based on the so-called "saboteurs" method. Results obtained for benchmark programs executed by a widely used commercial 8-bit microprocessor, allow to validate both approaches which provide inputs for an original error rate prediction methodology. The comparison of predictions to measured error rates issued from radiation ground testing validates the proposed error rate prediction approach.