Clocking strategies and scannable latches for low power appliacations
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Conditional pre-charge techniques for power-efficient dual-edge clocking
Proceedings of the 2002 international symposium on Low power electronics and design
Low power integrated scan-retention mechanism
Proceedings of the 2002 international symposium on Low power electronics and design
Clocking and Clocked Storage Elements in Multi-GHz Environment
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Optimization of scannable latches for low energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Clocking and clocked storage elements in a multi-gigahertz environment
IBM Journal of Research and Development
High-performance and low-power conditional discharge flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-edge triggered storage elements and clocking strategy for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Double edge triggered Feedback Flip-Flop in sub 100NM technology
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors
Proceedings of the 2006 international symposium on Low power electronics and design
Conditional data mapping flip-flops for low-power and high-performance systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
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An improved design of a hybrid latch flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and reduces the power consumption and delay of the circuit resulting in a total power-delay-product improvement of about 20%. It also exhibits better soft-clock edge properties compared to the original circuit. This is accomplished by careful design of keeper elements and introducing the feedback path to suppress unnecessary transitions in the circuit. The new design introduces an insignificant area increase.