Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
Optimizing pipelines for power and performance
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Hybrid latch Flip-Flop with Improved Power Efficiency
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
A 65-nm pulsed latch with a single clocked transistor
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
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We have reported previously [1] a low-swing latch (LSL) with superior performance-power tradeoff compared to the conventional pass-gate master-slave latch. In this paper, hardware results are presented for the proposed LSL with pulsed clock waveforms. The motivation is to combine low-voltage swing with pulsed signals to further reduce overall system power in high-frequency microprocessors. We have designed a 65-bit accumulator loop experiment to mimic a microprocessor pipeline stage. The local clock buffer design features a mode switch to toggle between two-phase (c1/c2) master-slave clocking and one-phase pulsed (c2 only) clocking. Our data show that 15-25% system power saving can be achieved in pulsed mode compared to non-pulsed mode. Power contribution from individual components is also presented.