Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Conditional pre-charge techniques for power-efficient dual-edge clocking
Proceedings of the 2002 international symposium on Low power electronics and design
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Digital System Clocking: High-Performance and Low-Power Aspects
Circuits and Technology for Digital's StrongARM(tm) and ALPHA Microprocessors
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Hybrid latch Flip-Flop with Improved Power Efficiency
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Dynamic Flip-Flop with Improved Power
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Optimal Sequencing Energy Allocation for CMOS Integrated Systems
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
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An overview of clocking and design of clocked storage elements is presented. Systematic design of Flip-Flop is explained as well as "time borrowing" and absorption of clock uncertainties. We show how different clocked storage elements should be compared against each other. The issues related to power consumption and low-power designs are presented.