Double edge triggered Feedback Flip-Flop in sub 100NM technology

Authors:
S. H. Rasouli;A. Amirabadi;A. Seyedi;A. Afzali-Kusha
Affiliations:
University of Tehran, Tehran, Iran;University of Tehran, Tehran, Iran;University of Tehran, Tehran, Iran;University of Tehran, Tehran, Iran
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

Citing 2
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Fundamentals of modern VLSI devices

Fundamentals of modern VLSI devices
Hybrid latch Flip-Flop with Improved Power Efficiency

SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design

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Abstract

In this paper, a new flip-flop called Double-edge triggered Feedback Flip-Flop (DFFF) is proposed. The dynamic power consumption of DFFF is reduced by avoiding unnecessary internal node transition. The subthreshold current in the flip-flops is very low compared to other structures. Reducing the number of transistor in the stack and increasing the number of charge path leads to higher operational speed compared to others flip-flops. The simulation results show an improvement of 44% in the speed and 45% in the static leakage power.