Low clock swing d flip-flops design by using output control and MTCMOS

Authors:
Saihua Lin;Hongli Gao;Huazhong Yang
Affiliations:
Electronic Engineering Department, Tsinghua University, Beijing, China;Electronic Engineering Department, Tsinghua University, Beijing, China;Electronic Engineering Department, Tsinghua University, Beijing, China
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

By using output control and MTCMOS techniques, we propose two low power low clock swing D flip-flops. Experimental results show that the leakage power of the proposed flip flops can be reduced more than an average of 59% in standby mode and in active mode the total power consumption can be reduced more than an average of 53% while the delay time stays the same. It is also show that the proposed D flip-flops can work even when the clock swing is nearly as low as Vdd/3, though the delay time is much increased.