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Real-time dynamic voltage scaling for low-power embedded operating systems
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Power-aware operating systems for interactive systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy aware task scheduling with task synchronization for embedded real time systems
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Priority Inheritance Protocols: An Approach to Real-Time Synchronization
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The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Performance Comparison of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
Processor Voltage Scheduling for Real-Time Tasks with Non-Preemptible Sections
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Balancing batteries, power, and performance: system issues in cpu speed-setting for mobile computing
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SOSP '03 Proceedings of the nineteenth ACM symposium on Operating systems principles
Dynamic Integrated Scheduling of Hard Real-Time, Soft Real-Time and Non-Real-Time Processes
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Power-Aware Scheduling for Periodic Real-Time Tasks
IEEE Transactions on Computers
On Energy-Constrained Real-Time Scheduling
ECRTS '04 Proceedings of the 16th Euromicro Conference on Real-Time Systems
CPU scheduling for statistically-assured real-time performance and improved energy efficiency
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Energy-efficient, utility accrual scheduling under resource constraints for mobile embedded systems
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On bounding energy consumption in dynamic, embedded real-time systems
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OSDI'00 Proceedings of the 4th conference on Symposium on Operating System Design & Implementation - Volume 4
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Energy-efficient dynamic task scheduling algorithms for DVS systems
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Energy aware dynamic voltage and frequency selection for real-time systems with energy harvesting
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We implement and experimentally evaluate the timeliness and energy consumption behaviors of fourteen Real-Time Dynamic Voltage and Frequency Scaling (RT-DVFS) schedulers on two hardware platforms. The schedulers include CC-EDF, LA-EDF, REUA, DRA, and AGR1, among others, and the hardware platforms include the Intel i5 processor and the AMD Zacate processor. Our studies reveal that measuring the CPU power consumption as the cube of CPU frequency -- as often done in the simulation-based RT-DVFS literature -- ignores the idle state CPU power consumption, which is significantly smaller than the active power consumption. Consequently, power savings obtained by optimizing active power (i.e., RT-DVFS) is offset by completing tasks sooner by running at high frequency and quickly transitioning to the idle state (i.e., no DVFS). Thus, the active power consumption savings of the RT-DVFS techniques' revealed by our measurements are significantly smaller than their simulation-based savings reported in the literature.