Analysis of power dissipation in double edge-triggered flip-flops

Authors:
Antonio G. M. Strollo;Ettore Napoli;Carlo Cimino
Affiliations:
Univ. of Naples, Naples, Italy;Univ. of Naples, Naples, Italy;Univ. of Naples, Naples, Italy
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Year:
2000

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Abstract

A comprehensive analysis of double edge triggered (DET) flip-flops' power dissipation, taking into account input signal statistics, is presented in this paper. It is shown that using DET instead of a single edge-triggered flip-flop may result in significant energy savings if the input signal has reduced activity. On the other hand, the high switching rate of DET internal nodes may result in larger power dissipation if the input signal has a high transition probability or significant glitching.