Unified gated flip-flops for reducing the clocking power in register circuits

Authors:
Takumi Okuhira;Tohru Ishihara
Affiliations:
Kyushu University, Fukuoka, Japan;Kyoto University, Kyoto, Japan
Venue:
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Year:
2011

Citing 9
Cited 0

Power minimization in IC design: principles and applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)
New clock-gating techniques for low-power flip-flops

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Power minimization of functional units partially guarded computation

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance

ACM Transactions on Computer Systems (TOCS)
Power Aware Design Methodologies

Power Aware Design Methodologies
Automatic Insertion of Gated Clocks at Register Transfer Level

VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture

ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
A Small, Fast and Low-Power Register File by Bit-Partitioning

HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs

Proceedings of the 2011 international symposium on Physical design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Since the clocking power consumption in today's processors is considerably large, reducing the clocking power consumption contributes to the reduction of the total power consumption in the processors. Recently, a gated flip-flop is proposed for reducing the clocking power consumption of flip-flop circuits. The gated flip-flop employs a clock-gating circuit which cuts off an internal clock signal if the data stored in the flip-flop does not need to be updated. Although this reduces the clocking power consumption, the power dissipated in the clock-gating circuit is still large. For reducing the power dissipated in the clock-gating circuit, this paper proposes a technique for unifying the multiple clockgating circuits, which reduces the overhead of the clock-gating circuit. Post-layout simulation results obtained using a commercial embedded processor which employs our unified gated flip-flop demonstrate that our technique reduces the power consumption of a core part of the processor by 25% on average and 33% at the best case compared to the same processor with the conventional gated flip-flop.