Instruction set synthesis with efficient instruction encoding for configurable processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Unified gated flip-flops for reducing the clocking power in register circuits
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Processor energy characterization for compiler-assisted software energy reduction
Journal of Electrical and Computer Engineering
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A new integrated system to design and generate a configurable embedded processor for multimedia applications has been developed. The system, "Media embedded Processor Integrator", provides a distinctive feature that generates development tools, such as compilers and simulators, not only for the configurable embedded processor but also for its template based extensible VLIW co-processor.This paper describes the architecture and the function of the "Media embedded Processor Integrator" especially focusing on how the system treats the VLIW co-processor extension. In order to determine an ISA for a 3-way VLIW co-processor for image recognition as an example, several different sets of ISA were evaluated and compared for the best performance using corresponding compilers and simulators, which were generated by the system. The system greatly contributed to reduce this entire ISA definition process.