VLSI array processors
Practical low power digital VLSI design
Practical low power digital VLSI design
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Automating RT-level operand isolation to minimize power consumption in datapaths
DATE '00 Proceedings of the conference on Design, automation and test in Europe
New clock-gating techniques for low-power flip-flops
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Low power design challenges for the decade (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Layout-driven memory synthesis for embedded systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer Organization and Design
Computer Organization and Design
Improving the Efficiency of Memory Partitioning by Address Clustering
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Battery-powered digital CMOS design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register transfer level power optimization with emphasis on glitch analysis and reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Multi-Shared Register File Structure for VLIW Processors
Journal of Signal Processing Systems
The optimal fan-out of clock network for power minimization by adaptive gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, low power architectures of register files on register-transfer level (RTL) are presented. The proposed architectures are implemented using a standard hardware description language (HDL) and can be synthesized within a commercial semi-custom design flow. The presented register file architectures are ideally suited for synthesizable processor cores or IP blocks. It is shown, that significant power savings of register files can be achieved, if a clock gating scheme for register files different from the one usually applied is used. As an alternative, an architecture with register isolation is presented. The third proposed register file architecture is based on interleaving known from signal processing implementations. Although, interleaving is usually applied to multichannel algorithms, it is shown that this architecture can also be applied to certain single channel cases. Experimental results of all three register file architectures prove that a significant power reduction can be achieved.