Battery-aware instruction generation for embedded processors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Battery optimization vs energy optimization: which to choose and when?
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Low power synthesizable register files for processor and IP cores
Integration, the VLSI Journal - Special issue: Low-power design techniques
VLIW instruction scheduling for minimal power variation
ACM Transactions on Architecture and Code Optimization (TACO)
Modulation selection from a battery power efficiency perspective: a case study of PPM and OOK
WCNC'09 Proceedings of the 2009 IEEE conference on Wireless Communications & Networking Conference
Low power synthesizable register files for processor and IP cores
Integration, the VLSI Journal - Special issue: Low-power design techniques
Modulation selection from a battery power efficiency perspective
IEEE Transactions on Communications
Relay selection from a battery energy efficiency perspective
MILCOM'09 Proceedings of the 28th IEEE conference on Military communications
An analytical model for predicting the remaining battery capacity of lithium-ion batteries
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utilization factor) decreases as the average discharge current from the battery increases. The implication is that the battery life is a superlinear function of the average discharge current. Next we show that even if the average discharge current remains the same, different discharge current profiles (distributions) may result in very different battery lifetimes. In particular, the maximum battery life is achieved when the variance of the discharge current distribution is minimized. Analytical derivations and experimental results underline the importance of the correct modeling of the battery-hardware system as a whole and provide a more accurate basis (i.e., the battery discharge times delay product) for comparing various low-power optimization methodologies and techniques targeted toward battery-powered electronics. Finally, we calculate the optimal value of V/sub dd/ for a battery-powered VLSI circuit so as to minimize the product of the battery discharge times circuit delay.