OFDM Wireless LANs: A Theoretical and Practical Guide
OFDM Wireless LANs: A Theoretical and Practical Guide
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
Low-power VLSI synthesis of DSP systems
Integration, the VLSI Journal
Power-Delay Metrics Revisited for 90nm CMOS Technology
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Tunable Wordlength Architecture for a Low Power Wireless OFDM Demodulator
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder
Journal of Signal Processing Systems
Test Enabled Process Tuning for Adaptive Baseband OFDM Processor
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Design of variable wordlength viterbi decoder in BICM-OFDM systems
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
IEEE Transactions on Consumer Electronics
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This paper describes the design of a new, variable wordlength, soft-decision Viterbi decoder that can significantly reduce power dissipation in wireless local area network (LAN) hardware. By taking into account the dynamic range of the time-varying channel coefficients, the quantization level is adjusted to suit the observed instantaneous link quality, i.e., the decoder wordlength is adjusted to maintain efficient throughput requirements and low power dissipation. A dynamic voltage scaling is applied with a variable wordlength to significantly reduce power consumption in the soft-decision Viterbi decoder. Unlike the conventional 8-bit fixed-wordlength decoder, our radix-4 Viterbi decoder can reduce power consumption by up to 35% under AWGN and multipath fading channel conditions.