Static Rate-Optimal Scheduling of Iterative Data-Flow Programs Via Optimum Unfolding
IEEE Transactions on Computers
Error control systems for digital communication and storage
Error control systems for digital communication and storage
Low-power architectural synthesis and the impact of exploiting locality
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Exploiting regularity for low-power design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Synthesis of folded pipelined architectures for multirate DSP algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Power Digital CMOS Design
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Variable wordlength soft-decision Viterbi decoder for power-efficient wireless LAN
Integration, the VLSI Journal
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In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this true expect for portable, battery-operated applications, where power consumption has perhaps superceded speed and area, which are the overriding implementation constraints. This adds another degree of freedom and complexity to the design process, and mandates the need for design techniques that address power, as well as area and speed. This paper proposes several low-power synthesis techniques for VLSI implementation of DSP systems both at the algorithmic and architectural levels. Low-power implementation of the Viterbi decoder using register-exchange is proposed. Conceptually, the register-exchange method is simpler and faster than the trace-back method. Reduction in switching activity at one or both inputs of the multipliers is a key to the reduction of power consumption in FIR filters. The switching activity can be reduced by the use of a transpose structure and by time multiplexing of an unfolded filter. The retiming approach is then used to facilitate the constrained operational schedule of different functional units. In the proposed techniques, about 20% in the overall implementation of Viterbi decoder and up to 80% in the implementation of folded FIR filters saving in power consumption has been reported.