Power Optimization of Parallel Multipliers in Systems with Variable Word-Length
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Design of variable wordlength viterbi decoder in BICM-OFDM systems
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
Exploiting finite precision information to guide data-flow mapping
Proceedings of the 47th Design Automation Conference
Variable wordlength soft-decision Viterbi decoder for power-efficient wireless LAN
Integration, the VLSI Journal
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We present a low power architecture that dynamically controls wordlengths in a wireless OFDM demodulator. Finding the optimum wordlength for digital circuit systems is difficult because the trade-off between the hardware cost and system performance is not conclusive. Actual circuit systems have large wordlengths at the circuit design level to avoid calculation errors caused by a lack of dynamic range. This indicates that power dissipation can still be reduced under better conditions. We propose a tunable wordlength architecture that dynamically changes its own wordlength according to the communication environment. The proposed OFDM demodulator measures error vector magnitudes (EVMs) from de-modulated signals and tunes the wordlength to satisfy the required quality of communication by monitoring the EVM performance. The demodulator can reduce dissipated energy by a maximum of 32 and 24% in AWGN and multipath fading channels.