Power-Delay Metrics Revisited for 90nm CMOS Technology

Authors:
Dipanjan Sengupta;Resve Saleh
Affiliations:
University of British Columbia, Canada;University of British Columbia, Canada
Venue:
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Year:
2005

Citing 6
Cited 3

A survey of design techniques for system-level dynamic power management

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Energy reduction techniques for multimedia applications with tolerance to deadline misses

Proceedings of the 40th annual Design Automation Conference
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction

Proceedings of the conference on Design, automation and test in Europe
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits

ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Extremely Low-Power Logic

Proceedings of the conference on Design, automation and test in Europe - Volume 1
Analysis and Design of Digital Integrated Circuits

Analysis and Design of Digital Integrated Circuits

A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A design-specific and thermally-aware methodology for trading-off power and performance in leakage-dominant CMOS technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variable wordlength soft-decision Viterbi decoder for power-efficient wireless LAN

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

Recently, designers have been using the energy-delay product as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more traditional power-delay product. As the industry moves to 90nm technology, with higher leakage currents, it is an appropriate time to revisit existing design metrics. In this paper, we provide a more general view of power and delay metrics for design optimization and then illustrate how these metrics can be used. To do so, a re-evaluation of the metrics, based on the past and future trends, is carried out and a set of new metrics is proposed. Interestingly, the dominance of leakage power at 90nm technology and beyond tends to reduce the feasible operation region. We also establish a fundamental relationship between the optimal operating points and the generalized design metrics. Moreover, our initial findings indicate that some designs may need to leak more than expected to achieve certain design targets, running somewhat counter to conventional wisdom.