Silicon Single-Electron Devices and Their Applications
ISMVL '00 Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic
Biotechnology: germs that build circuits
IEEE Spectrum
Power-Delay Metrics Revisited for 90nm CMOS Technology
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Hi-index | 0.00 |
For extremely Low-power Logic, three very new and promising techniques will be described. The first are methods on circuit and system level for reduced supply voltages. In large logic blocks, interconnect becomes a main issue, that could be solved by on-chip optical interconnect. Nano-devices will also be presented, as a possibility to compute with nearlyzero power, and compared to future 10 nanometers transistors.