Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies

Authors:
A. Raychowdhury;B. C. Paul;S. Bhunia;K. Roy
Affiliations:
Purdue University, IN;Purdue University, IN;Case Western Reserve University, OH;Purdue University, IN
Venue:
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Year:
2006

Citing 2
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Device and circuit design challenges in the digital subthreshold region for ultralow-power applications

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Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic

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Abstract

This paper presents a novel design methodology for ultralow power design (in bulk and double-gate SOI technology) using subthreshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of MHz). It has been shown that a complete co-design at all levels of hierarchy (device, circuit and architecture) is necessary to reduce the overall power consumption. Simulation results of co-design on a five-tap FIR filter shows ~2.5x (for bulk) and ~3.8x (for SOI) improvement in throughput at iso-power compared to a conventional design. It has been further demonstrated that the double-gate SOI technology is better suited for sub-threshold operation.