DRG-cache: a data retention gated-ground cache for low power
Proceedings of the 39th annual Design Automation Conference
Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
Characterizing and modeling minimum energy operation for subthreshold circuits
Proceedings of the 2004 international symposium on Low power electronics and design
Proceedings of the 2006 international symposium on Low power electronics and design
Analysis and optimization of sleep modes in subthreshold circuit design
Proceedings of the 44th annual Design Automation Conference
Exploiting STI stress for performance
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Stress aware layout optimization
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
| Hi-index | 0.00 |
Supply noise is a critical problem for the robust operation of integrated circuits at ultra low voltage regimes. Although decoupling capacitance is a traditional solution, the reduction of gate capacitance at subthreshold voltage can cause area overhead. In this paper, we propose a decoupling capacitor design strategy to reduce area overhead. The strategy consists of two parts: 1) enhancing gate capacitance through circuit optimizations and 2) using remote decoupling capacitors. Remote decoupling capacitors, which can be placed far from the block to compensate, can minimize the area overhead of the capacitance-enhancing optimizations. They also exploit less utilizable silicon area. The proposed strategy improves the capacitance density by 6.1 x without extra process steps, compared to the conventional approach. The gained robustness may be traded off for higher energy efficiency.