Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Statistical clock skew modeling with data delay variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Analysis and mitigation of variability in subthreshold design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Ultra-low-power DLMS adaptive filter for hearing aid applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Clock network design for ultra-low power applications
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuits
Proceedings of the 49th Annual Design Automation Conference
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This paper describes an interconnect technique for sub-threshold circuits to improve global wire delay and reduce the delay variation due to PVT fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from sub-threshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. A clock distribution network using the proposed drivers shows an 89% reduction in 3σ clock skew value. A 0.4V test chip has been fabricated in a 0.18μm 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6X faster switching speed and 2.4X less delay sensitivity under temperature variations.