Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Leakage power reduction using stress-enhanced layouts
Proceedings of the 45th annual Design Automation Conference
STEEL: a technique for stress-enhanced standard cell library design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On stress aware active area sizing, gate sizing, and repeater insertion
Proceedings of the 2009 international symposium on Physical design
STI stress aware placement optimization based on geometric programming
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Mechanical stress aware optimization for leakage power reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Closed-form modeling of layout-dependent mechanical stress
Proceedings of the 47th Design Automation Conference
Stress aware layout optimization leveraging active area dependent mobility enhancement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
D-A converter based variation analysis for analog layout design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuits
Proceedings of the 49th Annual Design Automation Conference
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Process-induced mechanical stress is used to enhance carrier transport and achieve higher drive currents in current CMOS technologies. In this paper, we study how stress-induced performance enhancements are affected by layout properties and suggest guidelines for improving layouts so that performance gains are maximized. All MOS devices in this work include STI and nitride stress liners as sources of stress. Additionally, the PMOS devices incorporate the stress effects caused by the embedded SiGe S/D layer common in today's processes. First, we study how stress and drive current depend on layout parameters such as active area length and contact placement. We develop an intuition for the drive current dependency on these parameters and propose simple guidelines to improve a layout while considering mechanical stress effects. We then use these guidelines to improve the standard cell layouts in a 65nm industrial library. Experimental results show that we can enhance NMOS and PMOS drive currents by ~5% and ~12%, respectively, while only increasing NMOS leakage current by 1.48X and PMOS leakage current by 3.78X. By applying our guidelines to a 3-input NOR gate and a 3-input NAND gate, we are able to achieve a ~13.5% PMOS drive current improvement in the NOR gate and a ~7% NMOS drive current improvement in the NAND gate, without increasing cell area in either case