Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Processors for Mobile Applications
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
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ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
An ultra low-power processor for sensor networks
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Analysis and mitigation of variability in subthreshold design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
A dual-processor solution for the MAC layer of a software defined radio terminal
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
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IBM Journal of Research and Development - Advanced silicon technology
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CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
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A low-power parallel design of discrete wavelet transform using subthreshold voltage technology
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Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
ACM Transactions on Architecture and Code Optimization (TACO)
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Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
An accelerator-based wireless sensor network processor in 130nm CMOS
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Energy-efficient subthreshold processor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation resilient adaptive controller for subthreshold circuits
Proceedings of the Conference on Design, Automation and Test in Europe
LATONA: an advanced server architecture for ubiquitous sensor network
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Hybrid super/subthreshold design of a low power scalable-throughput FFT architecture
Transactions on High-Performance Embedded Architectures and Compilers IV
Assessing the performance limits of parallelized near-threshold computing
Proceedings of the 49th Annual Design Automation Conference
Design of energy-efficient, adaptable throughput systems at near/sub-threshold voltage
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Optimization for real-time systems with non-convex power versus speed models
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interactive multi-frame reconstruction for mobile devices
Multimedia Tools and Applications
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Sensor network processors and their applications are a growing area of focus in computer system research and design. Inherent to this design space is a reduced processing performance requirement and extremely high energy constraints, such that sensor network processors must execute low-performance tasks for long durations on small energy supplies. In this paper, we demonstrate that subthreshold-voltage circuit design (400 mV and below) lends itself well to the performance and energy demands of sensor network processors. Moreover, we show that the landscape for microarchitectural energy optimization dramatically changes in the subthreshold domain. The dominance of leakage power in the subthreshold regime demands architectures that i) reduce overall area, ii) increase the utility of transistors, while iii) maintaining acceptable CPI efficiency. We confirm these observations by performing SPICE-level analysis of 21 sensor network processors and memory architectures. Our best sensor platform, implemented in 130nm CMOS and operating at 235 mV, only consumes 1.38 pJ/instruction, nearly an order of magnitude less energy than previously published sensor network processor results. This design, accompanied by bulk-silicon solar cells for energy scavenging, has been manufactured by IBM and is currently being tested.