Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
Energy Optimization of Subthreshold-Voltage Sensor Network Processors
Proceedings of the 32nd annual international symposium on Computer Architecture
Validity of the single processor approach to achieving large scale computing capabilities
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Digital Integrated Circuits
Dark silicon and the end of multicore scaling
Proceedings of the 38th annual international symposium on Computer architecture
ACM SIGARCH Computer Architecture News
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Supply voltage scaling has stagnated in recent technology nodes, leading to so-called "dark silicon." In this paper, we investigate the limit of voltage scaling together with task parallelization to maintain task completion latency. When accounting for parallelization overheads, minimum task energy is obtained at "near threshold" supply-voltages across 6 commercial technology nodes and provides 4X improvement in overall CMP performance.