Energy dissipation reduction of a cardiac event detector in the Sub-Vt

Authors:
Joachim Neves Rodrigues;Omer Can Akgun;Puneet Acharya;Adolfo de la Calle;Yusuf Leblebici;Viktor Öwall
Affiliations:
EIT, Lund University, Lund, Sweden;EPFL, STI-IEL-LSM, Lausanne, Switzerland;EIT, Lund University, Lund, Sweden;EIT, Lund University, Lund, Sweden;EPFL, STI-IEL-LSM, Lausanne, Switzerland;EIT, Lund University, Lund, Sweden
Venue:
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2009

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Abstract

This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the energy efficiency in the sub-threshold (sub-VT) domain. The design is synthesized in 65 nm low leakage-high threshold CMOS technology, and it is shown that folding reduces the area cost by 30.6 %. Folding decreases energy dissipation of the circuit by 14.4 % in the sub-VT regime, where the circuit dissipates 3.3 pJ per sample at VDD=0.26 V.