Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Proceedings of the 43rd annual Design Automation Conference
Variation-driven device sizing for minimum energy sub-threshold circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Utilizing reverse short channel effect for optimal subthreshold circuit design
Proceedings of the 2006 international symposium on Low power electronics and design
Energy-efficient subthreshold processor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Sub-threshold operation has been proved to be successful to achieve minimum energy consumption. It is well known that the sub-threshold device sizing is different from super-threshold due to different current behavior. The previously reported sub-threshold sizing methods assume that the current is proportional to the transistor width. However, we have found that the inverse narrow width effect has a significant influence on the threshold voltage in the sub-threshold region, causing non-proportional current-width relationship. Sizing without considering this effect may result in significant imbalance in the rise and fall delay which degrades the performance, power consumption and the functional yield of the design. We have proposed a new sub-threshold sizing method to balance the rise and fall delay by taking into account the influence of inverse narrow width effect while minimizing the transistor size. Compared with the previous sub-threshold sizing method the delay and power-delay-product (PDP) are reduced by up to 35.4% and 73.4% with up to 57% saving in the area. Further, due to symmetric rise and fall delay the minimum operating voltage can be lowered by 8% which leads to another 16% of energy reduction.