Analysis and mitigation of variability in subthreshold design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Identifying, tabulating, and analyzing contacts between branched neuron morphologies
IBM Journal of Research and Development
Pulse-Type Hardware Neural Network with Two Time Windows in STDP
Advances in Neuro-Information Processing
Modeling Spiking Neural Networks on SpiNNaker
Computing in Science and Engineering
Synchrony detection and amplification by silicon neurons with STDP synapses
IEEE Transactions on Neural Networks
Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
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Spike timing dependent plasticity (STDP) forms the basis of learning within neural networks. STDP allows for the modification of synaptic weights based upon the relative timing of pre- and post-synaptic spikes. A compact circuit is presented which can implement STDP, including the critical plasticity window, to determine synaptic modification. A physical model to predict the time window for plasticity to occur is formulated and the effects of process variations on the window is analyzed. The STDP circuit is implemented using two dedicated circuit blocks, one for potentiation and one for depression where each block consists of 4 transistors and a polysilicon capacitor. SpectreS simulations of the back-annotated layout of the circuit and experimental results indicate that STDP with biologically plausible critical timing windows over the range from 10@?s to 100ms can be implemented. Also a floating gate weight storage capability, with drive circuits, is presented and a detailed analysis correlating weights changes with charging time is given.