Analog Integrated Circuits and Signal Processing - Special issue: low-voltage low-power analog integrated circuits
Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Analysis and mitigation of variability in subthreshold design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Integrated Circuit Design for High-Speed Frequency Synthesis (Artech House Microwave Library)
Integrated Circuit Design for High-Speed Frequency Synthesis (Artech House Microwave Library)
7.95mW 2.4GHz Fully-Integrated CMOS Integer N Frequency Synthesizer
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
A very-high output impedance charge pump for low-voltage low-power PLLs
Microelectronics Journal
The Martian man: a heuristic approach on robots to mars
ROBIO'09 Proceedings of the 2009 international conference on Robotics and biomimetics
A low-voltage low-power injection-locked oscillator for wearable health monitoring systems
Analog Integrated Circuits and Signal Processing
Quantifying the channel quality for interference-aware wireless sensor networks
ACM SIGBED Review - Special Issue on the 10th International Workshop on Real-time Networks (RTN 2011)
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In this article, the architectural choices and design of a fully integrated integer-N frequency synthesizer operating in the 902---928 MHz Industrial, Scientific and Medical (ISM) band is presented. This frequency synthesizer, optimized for ultra-low power operation, is being integrated in the transceiver of an implantable wireless sensing microsystem (IWSM), which is dedicated to in vivo monitoring of biological parameters such as temperature, pressure, pH, oxygen, and nitric oxide concentrations. This phase-locked loop-based synthesizer includes a 1.830 GHz LC voltage-controlled oscillator (VCO) using a 10 nH on chip inductor. Varactors are implemented using P+ in N-well diodes for their linearity and high quality factor. The transistors of the VCO are operated in moderate inversion, and their bias point was chosen using the g m/I d design methodology. The output of the VCO, operating at twice the ISM frequency band, is divided by 2 to generate differential, quadrature versions of the carrier. Power minimization of the programmable divider was achieved by designing the latches and flip-flops using appropriate circuit techniques such as True Single Phase Clocking (TSPC) and first-type Dynamic Single Transistor Clocking (DSTC1) depending on their operating frequency. The power consumption of the proposed synthesizer is 580 μW under 1 V; almost an order of magnitude lower compared to that of recent synthesizer designs having a similar architecture.